The present invention generally relates to semiconductor devices, and more particularly to field effect transistor (FET) devices including FinFET structures having enhanced channel mobility, and a method for making the same.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. At the core of planar FETs, a channel region is formed in an n-doped or p-doped semiconductor substrate on which a gate structure is formed. Depending whether the on-state current is carried by electrons or holes, the FET comes as an n-FET or a p-FET. The overall fabrication process is well known in the art, and includes forming a gate structure over a channel region connecting a source and a drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source and drain region. As integrated circuits continue to scale downward in size, fin field effect transistors (FinFETs) or tri-gate structures are becoming more widely used, primarily because FinFETs offer better performance than planar FETs at the same power budget. FinFETs are three dimensional (3-D), fully depleted metal-oxide semiconductor field effect transistor (MOSFET) devices having a fin structure formed from the semiconductor substrate material. The fins extent between the device source and drain enfolding the channel region forming the bulk of the semiconductor device. The gate structure is located over the fins covering the channel region. Such architecture allows for a more precise control of the conducting channel by the gate, significantly reducing the amount of current leakage when the device is in off state.
A common technique used in planar FETs manufacturing to enhance carrier mobility in the channel region is channel straining. Channel straining in planar FETs is usually achieved by filling source and drain recesses with a stressor material in order to induce a compressive or tensile strain to the channel region. In FinFET devices conventional channel straining methods are more difficult to apply mostly due to the small dimensions of FinFET elements. For example, in FinFET devices the fin structure cannot be recessed to form an embedded source and drain region as in planar FETs. Factors such as scaling of FinFET devices, FinFETs manufacturing materials and 3-D topography may impact effective channel straining if conducted using traditional straining techniques.